FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
SPI Stop/Sleep
Command
SPI CS
t
CS-STOP
tIDD-DGLT
33742 in Stop mode.
No IDD over IDD-DGLT
33742 in Normal
or Stand-by mode
33742 in Stop mode.
IDD over IDD-DGLT
Figure 11. Entering the Stop Mode
RST PIN DESCRIPTION
WATCHDOG SOFTWARE (RST AND WDOG)
(SELECTABLE WATCHDOG WINDOW OR
WATCHDOG TIME-OUT)
A 33742 output is available to perform a reset of the MCU.
Reset can happen from:
A watchdog is used in the SBC Normal and Standby
modes for monitoring the MCU operation. The watchdog
timer may be implemented as either a watchdog window or
watchdog time-out, selectable by SPI (TIM1 sub register, bit
WDW). Default operation is a watchdog window.
• VDD Falling Out of Range—If VDD falls below the reset
threshold (VRSTTH), the RST pin is pulled LOW until
VDD returns to the normal voltage.
• Power-ON Reset—At 33742 power-on or wake-up from
Sleep mode, the RST pin is maintained LOW until VDD
is within its operation range.
• Watchdog Time-out—If watchdog is not cleared, the
33742 will pull the RST pin LOW for the duration of the
reset time (tRSTDUR).
The watchdog period can be set from 10 ms to 350 ms
(TIM1 sub register, bits WDT0 and WDT1). When a watchdog
window is selected, the closed window is the first part of the
selected period, and the open window is the second part of
the period. (Refer to Timing Register (TIM1/2) beginning on
page 47.)
RST AND WDOG OPERATION
The watchdog can only be cleared within the open window
time period. Any attempt to clear watchdog in the closed
window will generate a reset. The watchdog is cleared
addressing the TIM1 sub register using the SPI
Table 8 describes watchdog and reset output modes of
operation. RST is activated in the event VDD fall or watchdog
is not triggered. WDOG output is active LOW as soon as RST
goes LOW and stays LOW as long as the watchdog is not
properly reset via SPI. The WDOG output pin is designed as
a push-pull structure that can drive off chip components
signaling, for instance, errant MCU operation.
Figure 12 illustrates the device behavior in the event the
TIM1 register in not properly accessed. In this case a
software reset occurs, and the WDOG pin is set LOW until
the TIM1 register is properly accessed.
Table 8. Watchdog and Reset Output Operation
Events
WDOG
RST Output
Output
Device Power-Up
VDD Normal, WDOG Properly Triggered
VDD < VRSTTH
LOW to HIGH
HIGH
LOW to HIGH
HIGH
HIGH
LOW
WDOG Time-out Reached
LOW (41)
LOW
Notes
41. WDOG stays LOW until the TIM1 register is properly addressed through SPI.
33742
Analog Integrated Circuit Device Data
Freescale Semiconductor
27
FREESCALE [ Freescale ]
