Package and Pin Listings
Figure 37 provides the AC test load for the SPI.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 37. SPI AC Test Load
Figure 38 and Figure 39 represent the AC timings from Table 54. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Figure 38 shows the SPI timings in slave mode (external clock).
SPICLK (Input)
tNEIXKH
tNEIVKH
Input Signals:
SPIMOSI
(See Note)
tNEKHOX
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 38. SPI AC Timing in Slave Mode (External Clock) Diagram
Figure 39 shows the SPI timings in master mode (internal clock).
SPICLK (Output)
tNIIXKH
tNIIVKH
Input Signals:
SPIMISO
(See Note)
tNIKHOX
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 39. SPI AC Timing in Master Mode (Internal Clock) Diagram
18 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions. The MPC8349EA is available
in a tape ball grid array (TBGA). See Section 18.1, “Package Parameters for the MPC8349EA TBGA” and
Section 18.2, “Mechanical Dimensions for the MPC8349EA TBGA.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
53
FREESCALE [ Freescale ]
