Power Characteristics
supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of
time that all input and output pins will actively be driven and cause contention and excessive current from
3A to 5A. In order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the
core voltage (V ) before the I/O voltage (GV , LV , and OV ) and assert PORESET before the
DD
DD
DD
DD
power supplies fully ramp up. In the case where the core voltage is applied first, the core voltage supply
must rise to 90% of its nominal value before the I/O supplies reach 0.7 V, see Figure 4.
Voltage
I/O Voltage (GVDD, LVDD, OVDD
)
Core Voltage (VDD, AVDD
)
0.7 V
90%
Time
Figure 4. Power Sequencing Example
I/O voltage supplies (GV , LV , and OV ) do not have any ordering requirements with respect to one
DD
DD
DD
another.
3 Power Characteristics
The estimated typical power dissipation for the MPC8349EA device is shown in Table 4.
1
Table 4. MPC8349EA Power Dissipation
,
3
Core Frequency (MHz) CSB Frequency (MHz) Typical at TJ = 65 Typical2
Maximum4
Unit
TBGA
333
333
166
266
133
300
150
333
166
266
133
333
2.0
1.8
2.1
1.9
2.3
2.1
2.4
2.2
2.4
2.2
3.5
3.0
2.8
3.0
2.9
3.2
3.0
3.3
3.1
3.3
3.1
4.6
3.2
2.9
3.3
3.1
3.5
3.2
3.6
3.4
3.6
3.4
5
W
W
W
W
W
W
W
W
W
W
W
400
450
500
533
6675, 6
1
The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 5.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
10
Freescale Semiconductor
FREESCALE [ Freescale ]
