RESET Initialization
1
Table 9. RESET Pins DC Electrical Characteristics (continued)
Parameter
Symbol
Condition
Min
Max
Unit
Output low voltage
V
IOL = 3.2 mA
—
0.4
V
OL
Notes:
1. This table applies for pins PORESET, HRESET, SRESET, and QUIESCE.
2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins.
5.2
RESET AC Electrical Characteristics
Table 10 provides the reset initialization AC timing specifications of the MPC8349EA.
Table 10. RESET Initialization Timing Specifications
Parameter
Min
Max
Unit
Notes
Required assertion time of HRESET or SRESET (input) to activate reset flow
32
32
—
—
tPCI_SYNC_IN
tCLKIN
1
2
Required assertion time of PORESET with stable clock applied to CLKIN when the
MPC8349EA is in PCI host mode
Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN
when the MPC8349EA is in PCI agent mode
32
—
tPCI_SYNC_IN
1
HRESET/SRESET assertion (output)
512
16
4
—
—
—
tPCI_SYNC_IN
tPCI_SYNC_IN
tCLKIN
1
1
2
HRESET negation to SRESET negation (output)
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is
in PCI host mode
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2] and
CFG_CLKIN_DIV) with respect to negation of PORESET when the MPC8349EA is
in PCI agent mode
4
—
tPCI_SYNC_IN
1
Input hold time for POR configuration signals with respect to negation of HRESET
0
—
4
ns
ns
—
3
Time for the MPC8349EA to turn off POR configuration signals with respect to the
assertion of HRESET
—
Time for the MPC8349EA to turn on POR configuration signals with respect to the
negation of HRESET
1
—
tPCI_SYNC_IN 1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. In PCI host mode, the primary clock is applied
to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is valid only in PCI host mode. See the MPC8349EA
PowerQUICC II Pro Integrated Host Processor Family Reference Manual.
3. POR configuration signals consist of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
14
Freescale Semiconductor
FREESCALE [ Freescale ]
