Feature Integration Technology Inc.
Fintek
Power-on strapping with internal pulled-up resistor will enable
CR03h (BIOS_ROM_EN, BIOS_WR_EN bit). If there is a
boot-ROM (BIOS), else if without boot-ROM, please use external
pulled-down 10K resister to disable this ROM_EN and WR_EN.
ROM_EN
GPIO0
IRQ1
General purpose I/O pin 0.
I/O24ts
(5V-tolerance)
38
39
40
VDD3v
VDD3v
VDD3v
Parallel Interrupt Requested Input 1. This pin is used for specific
K/B functions.
GPIO1
KBCS#
General purpose I/O pin 1.
I/O24t
(5V-tolerance)
Decode address 60h and 64h to generate chip selected signal.
Enable by KBEN# power-on setting.
GPIO2
MCCS#
GPIO3
IRQIN
General purpose I/O pin 2.
I/O24ts
(5V-tolerance)
Decode address 62h and 66h to generate chip selected signal.
Enable by KBEN# power-on setting.
General purpose I/O pin 3.
I/O24ts
(5V-tolerance)
62
63
64
VDD3v
VDD3v
VDD3v
It is programmable to transfer parallel IRQ input to serial IRQ,
Enable by KBEN# power-on setting.
GPIO4
PLED
General purpose I/O pin 4.
I/O24ts
(5V-tolerance)
Power LED output, the signal is at low state after system reset.
GPIO5
IRQ8
General purpose I/O pin 5.
I/O24ts
(5V-tolerance)
Parallel Interrupt Requested Input 8. This interrupt request is used
for specific RTC functions. Enable by RTCEN# power-on setting.
GPIO6
RTCCS#
General purpose I/O pin 6.
I/O24ts
(5V-tolerance)
65
66
VDD3v
VDD3v
Decode address 70h and 71h to generate chip selected signal.
Enable by RTCEN# power-on setting.
GPIO7
General purpose I/O pin 7.
I/O24ts
(5V-tolerance)
Decode SA [15-11] all are at “0” state initially and setting by CR04
Bit 6.
IOHCS#
INts
26
27
28
29
14.318M
VDD3v
VDD3v
VDD3v
VDD3v
14.318 MHz Clock Input.
(5V-tolerance)
O20
O20
14MOUT 1
14MOUT 2
14.318 MHz Buffer Output 1.
14.318 MHz Buffer Output 2.
GP20
PLED
General purpose I/O pin.
I/O24ts
(5V-tolerance)
Power LED output, the signal is at low state after system reset.
9
F85226
July, 2007
V0.25P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
