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F85226F 参数 Datasheet PDF下载

F85226F图片预览
型号: F85226F
PDF下载: 下载PDF文件 查看货源
内容描述: LPC到ISA桥 [LPC to ISA Bridge]
分类和应用: PC
文件页数/大小: 44 页 / 1073 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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Feature Integration Technology Inc.  
Fintek  
F85226  
PCI system reset used for the LPC bus. The Reset signal line can  
be connected to PCIRST# signal on the host.  
VDD3v  
14  
PCIRST#  
INts  
VDD3v  
VDD3v  
23  
22  
SERIRQ  
LDRQ#  
I/O24ts  
O24  
Serial IRQ Input/Output.  
Encoded DMA Request signal.  
Power Down. The signal is active low according to CR 44 Bit 7and  
wake-up enable by hardware setting. There are eight different  
power-down states (Power down Mode 3).  
24  
VDD3v  
PWRDN#  
INts  
6.4  
ISA interface  
Pin No.  
Pin Name  
Type  
PWR  
Description  
System Address Bus. These are the upper addresses that define  
the ISA’s byte address space (up to 1 M byte). The SA [19:17] are  
at tri-states during PCIRST#.  
SA[19:17]  
I/O24ts_u100k  
(5V-tolerance)  
58-56  
VDD3v  
54-51  
49-46  
44-41  
I/O24ts_u100k  
(5V-tolerance)  
System Address Bus. These define the ISA’s byte address space  
(up to 128K byte). The SD [16:0] are at tri-states during PCIRST#.  
SA[16:0]  
SD[15:0]  
VDD3v  
VDD3v  
35-31  
122-121  
119-114  
75-71  
I/O24ts_u100k  
(5V-tolerance)  
System Data Bus. These provide 16-bit data for devices to reside  
on the ISA Bus. The SD [15:0] are at tri-states during PCIRST#.  
69-67  
O24  
Address Enable. AEN is asserted during DMA cycles, driven high  
during F85226 initiated refresh cycles, driven low upon PCIRST#.  
59  
86  
84  
AEN  
VDD3v  
VDD3v  
VDD3v  
(5V-tolerance)  
I/O24ts_u100k  
(5V-tolerance)  
I/O Read. IOR# is asserted to request an ISA I/O slave to drive  
data onto the data bus.  
IOR#  
IOW#  
I/O24ts_u100k  
(5V-tolerance)  
I/O Write. IOW# is asserted to request an ISA I/O slave to accept  
data from the data bus.  
I/O Channel Ready. IOCHDRY asserted indicates that an ISA  
slave requires additional wait states. When the F85226 is an ISA  
slave, IOCHRDY is an output indicating additional wait states are  
required.  
I/O24ts  
(5V-tolerance)  
61  
IOCHRDY  
VDD3v  
ISA System Clock. SYSCLK offers the reference clock to the ISA  
bus. The frequency is generated from dividing PCICLK by 3 or 4  
(select by CR06 bit7).  
92  
77  
SYSCLK  
RSTDRV  
O24  
O24  
VDD3v  
VDD3v  
Reset Drive. RSTDRV asserted indicates to reset devices that  
reside on the ISA Bus while the PCIRST# has been asserted.  
5
F85226  
July, 2007  
V0.25P