Feature Integration Technology Inc.
Fintek
I/O24ts
(5V-tolerance)
16-bit I/O Chip Select. IOCS16# is asserted by 16-bit ISA I/O
devices to indicate that they support 16-bit I/O bus cycles.
11
12
76
IOCS16#
VDD3v
VDD3v
VDD3v
Memory Chip Select 16. MEMCS16# is asserted by 16-bit ISA
memory devices to indicate that the memory slave supports 16-bit
accesses.
I/O24ts
(5V-tolerance)
MEMCS16#
IOCHCK#
INts
I/O Channel Check. Asserted by an ISA device indicating an error
condition.
(5V-tolerance)
Zero Wait States. An ISA slave asserts ZEROWS# after its
address and command signals have been decoded to indicate
that the current cycle can be executed as an ISA zero wait state
cycle. ZEROWS# has no effect during 16-bit I/O cycles.
Unlatched Address. The LA [23:20] address lines are
bi-directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA [23:20] are outputs
when the F85226 owns the ISA Bus.
INts
81
OWS#
VDD3v
VDD3v
(5V-tolerance)
103-104
106-107
I/O24ts_u100k
(5V-tolerance)
LA[23:20]
LA[19:17]
Unlatched Address. The LA [19:17] address lines are
bi-directional. These address lines allow accesses to physical
memory on the ISA Bus up to 16 Mbytes. LA [19:17] are outputs
when the F85226 owns the ISA Bus.
108-109
111
I/O24ts_u100k
(5V-tolerance)
VDD3v
GP23,
GP21
GP22,
General purpose I/O pin.
O24
Standard (system) Memory Write. SMEMW# is asserted for
memory write accesses below 1MB.
82
83
SMEMW#
SMEMR#
VDD3v
VDD3v
(5V-tolerance)
O24
Standard (system) Memory Read. SMEMR# is asserted for
memory read accesses below 1 MB.
(5V-tolerance)
Refresh Cycle indicator. REFRESH# asserted indicates that a
refresh cycle is in progress, or ISA master requests F85226 to
generate a refresh cycle. The signal is at tri-stated upon
PCIRST#.
O24_u100k
(5V-tolerance)
91
REFRESH#
VDD3v
Bus Address Latch Enable. BALE asserted indicates when the
address (SA[19:0], LA[23:17]) and SBHE# are valid. The LA
[23:17] address lines are latched on the trailing edge of BALE.
BALE is driven by low upon PCIRST#.
I/O24ts_u100k
(5V-tolerance)
101
102
BALE
VDD3v
VDD3v
System Byte High Enable. SBHE# asserted indicates that
SD[15:8] will be used to transfer a byte. SBHE# is at an unknown
state upon PCIRST#.
I/O24ts_u100k
(5V-tolerance)
SBHE#
I/O24ts_u100k
(5V-tolerance)
Memory Read. MEMR# asserted indicates the current ISA bus
cycle is a memory read.
112
113
MEMR#
MEMW#
VDD3v
VDD3v
I/O24ts_u100k
(5V-tolerance)
Memory Write. MEMW# asserted indicates the current ISA bus
cycle is a memory write.
6
F85226
July, 2007
V0.25P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
