Feature Integration Technology Inc.
Fintek
The MASTER# input asserted indicates an ISA bus master is
driving the ISA bus. This signal is executed with DREQ line by an
ISA master to gain control of the ISA Bus.
INts
123
MASTER#
VDD3v
(5V-tolerance)
INts
98
97
96
94
93
78
10
9
IRQ3
VDD3v
VDD3v
VDD3v
VDD3v
VDD3v
VDD3v
VDD3v
VDD3v
VDD3v
VDD3v
VDD3v
Parallel Interrupt Requested Input 3.
Parallel Interrupt Requested Input 4.
Parallel Interrupt Requested Input 5.
Parallel Interrupt Requested Input 6.
Parallel Interrupt Requested Input 7.
Parallel Interrupt Requested Input 9.
Parallel Interrupt Requested Input 10.
Parallel Interrupt Requested Input 11.
Parallel Interrupt Requested Input 12.
Parallel Interrupt Requested Input 14.
Parallel Interrupt Requested Input 15.
(5V-tolerance)
INts
IRQ4
(5V-tolerance)
INts
IRQ5
(5V-tolerance)
INts
IRQ6
(5V-tolerance)
INts
IRQ7
(5V-tolerance)
INts
IRQ9
(5V-tolerance)
INts
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
(5V-tolerance)
INts
(5V-tolerance)
INts
8
(5V-tolerance)
INts
6
(5V-tolerance)
INts
7
(5V-tolerance)
DMA Request input 0. The DREQ asserted indicates that either a
slave DMA device is requesting DMA services or an ISA bus
master is requesting to use the ISA bus.
INts
3
DRQ0
VDD3v
(5V-tolerance)
INts
90
79
88
1
DRQ1
DRQ2
DRQ3
DRQ5
VDD3v
VDD3v
VDD3v
VDD3v
DMA Request input 1.
DMA Request input 2.
DMA Request input 3.
DMA Request input 5.
(5V-tolerance)
INts
(5V-tolerance)
INts
(5V-tolerance)
INts
(5V-tolerance)
7
F85226
July, 2007
V0.25P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
