Feature Integration Technology Inc.
Fintek
7. Function Description
7.1 LPC interface:
The F85226 implemented full functions that described in the LPC I/F 1.1 specification and transfers all
subtractive cycles from LPC bus to ISA interface for more ISA compatibility. The F85226 built in 16-bit IO/
Memory enhances transaction. Peripheral or Master devices can assert cycles that are not defined in
positive decode ranges of LPC Interface. All LPC bus signals use PCI electrical characteristics. The
following cycle types are supported by F85226.
z
z
z
z
IO read write (8 / 16 bit)
Memory read write (8 / 16 bit)
DMA read write (8/ 16 / 32 bit)
Firmware memory read write (only support size 8 or 16 bit).
eCycles:
S: Start Cycle
C: Command Type Cycle
Cycle Types
Encoding
Remark
S: 0x0h;
C: 0x0h
S: 0x0h;
C: 0x2h
S: 0x0h;
C: 0x4h
S: 0x0h;
C: 0x6h
S: 0x0h;
C: 0x8h
S: 0x0h;
C: 0xAh
S: 0xDh;
IO Read
Size: 8 bit and 16 bit in Enhanced mode, for LPC peripheral.
IO Write
Size: 8 bit and 16 bit in Enhanced mode, for LPC peripheral.
Size: 8 bit and 16 bit in Enhanced mode, for LPC peripheral and host.
Size: 8 bit and 16 bit in Enhanced mode, for LPC peripheral and host.
Size: 8, 16 and 32 bit, for LPC peripheral.
Memory Read
Memory Write
DMA Read
DMA Write
Size: 8, 16 and 32 bit, for LPC peripheral.
Booting Memory Read
Size: 8, 16, 32 and 1024 bit, for LPC peripheral.
Size: 8, 16, and 32 bit, for LPC peripheral.
Booting Memory Write
S: 0xEh;
Start:
The cycle indicates the beginning or abort of a transaction. When LFRAME# is asserted low and monitors
LAD[3:0] that determine frame type to enter a valid Start.
Cycle Type and Direction:
LPC host will issue the transaction cycle and direction by LAD[3:1] and LAD0 is always ignored.
10
F85226
July, 2007
V0.25P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
