F81867
4
3
2
1
0
VIN4_CONV_STS WC
VIN3_CONV_STS WC
VIN2_CONV_STS WC
VIN1_CONV_STS WC
5VSB
5VSB
5VSB
5VSB
5VSB
-
-
-
-
-
VIN4 voltage channel had finish converting
VIN3 voltage channel had finish converting
VIN2 voltage channel had finish converting
VIN1 voltage channel had finish converting
VCC voltage channel had finish converting
VCC_CONV_STS
WC
HM μC Interrupt Enable Register 1⎯ Offset 53h
Bit
Name
R/W Reset Default
Description
7-6
Reserved
-
-
-
Reserved
Generate an interrupt for μC when this bit is set to 1 and PECI
_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and
TSI_CONV_STS is 1.
5
PECI_INT_EN
R/W 5VSB
R/W 5VSB
0
4
3
2
TSI_INT_EN
Reserved
0
-
-
-
Reserved
Generate an interrupt for μC when this bit is set to 1 and
T2_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and
T1_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and
T0_CONV_STS is 1.
T2_INT_EN
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
1
0
T1_INT_EN
T0_INT_EN
0
0
HM μC Interrupt Enable Register 2⎯ Offset 54h
Bit
Name
R/W Reset Default
Description
Generate an interrupt for μC when this bit is set to 1 and VSB5V
_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and VBAT
_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and VSB
3V_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and VIN4
_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and VIN3
_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and VIN2
_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and VIN1
_CONV_STS is 1.
Generate an interrupt for μC when this bit is set to 1 and VCC
_CONV_STS is 1.
7
VSB5V_INT_EN
R/W
R/W
5VSB
5VSB
5VSB
5VSB
5VSB
5VSB
5VSB
5VSB
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
VBAT_INT_EN
VSB3V_INT_EN R/W
VIN4_INT_EN
VIN3_INT_EN
VIN2_INT_EN
VIN1_INT_EN
VCC_INT_EN
R/W
R/W
R/W
R/W
R/W
HM RAW Data Register 1⎯ Offset 55h
Bit
Name
R/W Reset Default
5VSB
Description
7-0
RAW_DATA_L
R
0
Low byte of HM converting raw data
HM RAW Data Register 2⎯ Offset 56h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
-
Reserved
228
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
