F81867
Select the source temperature for T1 OVT Limit.
0: Select T1 to be compared to Temperature 1 OVT Limit.
1: Select CPU temperature from PECI to be compared to
Temperature 1 OVT Limit.
5VSB
5-4 OVT_TEMP_SEL R/W
0
0
0
2: Select CPU temperature from AMD TSI or Intel PCH I2C to be
compared to Temperature 1 OVT Limit.
3: Select the MAX temperature from Intel PCH I2C to be
compared to Temperature 1 OVT Limit.
-
3-2
Reserved
R/W
Reserved
Select the source temperature for T1 High Limit.
0: Select T1 to be compared to Temperature 1 High Limit.
1: Select CPU temperature from PECI to be compared to
Temperature 1 High Limit.
1-0 HIGH_ TEMP_SEL R/W 5VSB
2: Select CPU temperature from AMD TSI or Intel PCH I2C to be
compared to Temperature 1 High Limit.
3: Select the MAX temperature from Intel PCH I2C to be
compared to Temperature 1 High Limit.
OVT and Alert Output Enable Register 1 ⎯ Offset 66h
Bit
Name
R/W Reset Default
Description
7
Reserved
R/W
-
0
Reserved
Enable temperature 2 alert event (asserted when temperature
over high limit)
5VSB
6
EN_T2_ALERT R/W
EN_T1_ALERT R/W
0
Enable temperature 1 alert event (asserted when temperature
over high limit)
5VSB
5VSB
5
4
0
0
Enable temperature 0 alert event (asserted when temperature
over high limit)
EN_T0_ALERT
R/W
-
3
2
Reserved
-
0
0
1
0
Reserved
5VSB
5VSB
EN_T2_OVT
EN_T1_OVT
EN_T0_OVT
R/W
R/W
Enable over temperature (OVT) mechanism of temperature2.
1
Enable over temperature (OVT) mechanism of temperature1.
Enable over temperature (OVT) mechanism of temperature0.
0
R/W 5VSB
Reserved ⎯Offset 67~69h
Bit
Name
R/W Reset Default
Description
7-0
Reserved
-
-
-
Reserved
231
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
