F81867
Temperature Real Time Status Register ⎯ Offset 62h
Bit
Name
R/W Reset Default
Description
7
Reserved
R/W
-
0
Reserved
Set when the TEMP2 exceeds the OVT limit. Clear when the
TEMP2 is below the “OVT limit –hysteresis” temperature.
Set when the TEMP1 exceeds the OVT limit. Clear when the
TEMP1 is below the “OVT limit –hysteresis” temperature.
3VCC
6
5
T2_OVT
T1_OVT
R/W
0
3VCC
R/W
0
Set when the TEMP0 exceeds the OVT limit. Clear when the
TEMP0 is below the “OVT limit –hysteresis” temperature.
4
3
T0_OVT
R/W
R/W
3VCC
-
0
0
Reserved
Reserved
Set when the TEMP2 exceeds the high limit. Clear when the
TEMP2 is below the “high limit –hysteresis” temperature.
Set when the TEMP1 exceeds the high limit. Clear when the
TEMP1 is below the “high limit –hysteresis” temperature.
3VCC
2
T2_EXC
R/W
0
1
0
T1_EXC
T0_EXC
R/W 3VCC
0
0
Set when the TEMP0 exceeds the high limit. Clear when the
TEMP0 is below the “high limit –hysteresis” temperature.
R/W
3VCC
Temperature BEEP Enable Register ⎯ Offset 63h
Bit
Name
Reserved
EN_ T2_
R/W Reset Default
Description
7
R/W
-
0
Reserved
If set this bit to 1, BEEP signal will be issued when TEMP2
exceeds OVT limit setting.
5VSB
6
5
R/W
0
OVT_BEEP
EN_ T1_
If set this bit to 1, BEEP signal will be issued when TEMP1
exceeds OVT limit setting.
5VSB
R/W
0
OVT_BEEP
EN_ T0_
OVT_BEEP
If set this bit to 1, BEEP signal will be issued when TEMP0
exceeds OVT limit setting.
4
3
R/W
R/W
5VSB
-
0
0
Reserved
EN_
Reserved
If set this bit to 1, BEEP signal will be issued when TEMP2
exceeds high limit setting.
5VSB
2
R/W
0
T2_EXC_BEEP
EN_
If set this bit to 1, BEEP signal will be issued when TEMP1
exceeds high limit setting.
1
0
R/W
R/W
5VSB
5VSB
0
0
T1_EXC_BEEP
EN_
T0_EXC_BEEP
If set this bit to 1, BEEP signal will be issued when TEMP0
exceeds high limit setting.
T1 OVT and High Limit Temperature Select Register ⎯ Offset 64h
Bit
Name
R/W Reset Default
R/W Reserved
Description
7-6
Reserved
-
0
230
Dec, 2011
V0.12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
