F81866A
TSI Offset Register ⎯ Index 0Dh
Bit
Name
R/W Reset Default
Description
This byte is used as the offset to be added to the CPU temperature
7-0
TSI_OFFSET
R/W 5VSB
0
reading of AMD_TSI.
The range of this register is -128 ~ 127ºC.
Configuration Register ⎯ Index 0Fh
Bit
7-2
1-0
Name
Reserved
R/W Reset Default
Description
-
-
0
0
Reserved.
Reserved for Fintek use only
DIG_RATE_SEL
R/W
5VSB
TSI, I2C Temperature 0 – Index E0h
Bit
Name
R/W
Reset Default
Description
This is the AMD TSI reading if AMD TSI enable.
And will be highest temperature among CPU, MCH and PCH if Intel
temperature interface enable. The range is 0~255ºC. To access this byte,
MCH_BANK_SEL must set to “0”.
TSI_TEMP0
R/W
5VSB
-
This byte is used as multi-purpose:
1. The received data of receive protocol.
7-0
2. The first received byte of read word protocol.
3. The 10th received byte of read block protocol.
4. The sent data for send byte protocol and write byte protocol.
5. The first send byte for write word protocol.
6. The first send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
I2C_DATA0
R/W
5VSB
8’h00
TSI, I2C Temperature 1 – Index E1h
Bit
Name
R/W
Reset Default
Description
This is the high byte of Intel temperature interface PCH reading. The
range is 0~255ºC.
TSI_TEMP1
R
5VSB
-
To access this byte, MCH_BANK_SEL should be set to “0”.
This byte is used as multi-purpose:
7-0
1. The second received byte of read word protocol.
2. The 11th received byte of read block protocol.
3. The second send byte for write word protocol.
4. The second send byte for write block protocol.
To access this byte, MCH_BANK_SEL should be set to “1”.
I2C_DATA1
R/W
5VSB
8’h00
48
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
