F81866A
IRQ_MODE1 and IRQ_MODE0 will select the UART2 interrupt mode if IRQ
sharing is enabled.
00 : Sharing IRQ active low Level mode.
01 : Sharing IRQ active high edge mode.
10 : Sharing IRQ active high Level mode.
1
0
IRQ_MODE0
IRQ_SHARE
R/W LRESET#
0
0
11 : Reserved.
This bit is effective at IRQ is sharing with the other device (IRQ_SHARE, bit 1).
0 : IRQ is not sharing with the other device.
1 : IRQ is sharing with the other device.
R/W LRESET#
7.11.6Clock Register ⎯ Index F2h
Bit
Name
R/W Reset Default
Description
7-2
Reserved
-
-
-
Reserved.
Select the clock source for UART2.
00: 1.8432MHz.
1-0
UART2_CLK_SEL R/W LRESET# 00b 01: 18.432MHz.
10: 24MHz.
11: 14.769MHz.
7.11.79bit-mode Slave Address Register ⎯ Index F4h
Bit
Name
R/W Reset Default
Description
This byte accompanying with SADEN will determine the given address and
broadcast address in 9-bit mode. The UART will response to both given and
broadcast address.
Following description determines the given address and broadcast address:
5. given address: If bit n of SADEN is “0”, then the corresponding bit of
SADDR is don’t care.
6. broadcast address: If bit n of ORed SADDR and SADEN is “0”, don’t care
that bit. The remaining bit which is “1” is compared to the received
address.
7-0
SADDR
R/W LRESET#
00h
Ex.
SADDR
SADEN
0101_1100b
1111_1001b
0101_1xx0b
1111_11x1b
Given Address
Broadcast Address
182
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
