F81866A
7.8.2Base Address High Register ⎯ Index 60h
Bit
Name
R/W Reset Default
Description
7-0
BASE_ADDR_HI
R/W 5VSB 00h The MSB of WDT base address.
7.8.3Base Address Low Register ⎯ Index 61h
Bit
Name
R/W Reset Default
R/W 5VSB 00h The LSB of WDT base address.
Description
Description
7-0
BASE_ADDR_LO
7.8.4Watchdog Control Configuration Register 1 ⎯ Index F5h
Bit
Name
R/W Reset Default
Reserved
7
Reserved
R
-
0
0
If watchdog timeout event occurred, this bit will be set to 1. Write a 1 to this
bit will clear it to 0.
6
WDTMOUT_STS
R/W 5VSB
If this bit is set to 1, the counting of watchdog time is enabled.
5
4
3
WD_EN
WD_PULSE
WD_UNIT
R/W 5VSB
R/W 5VSB
R/W 5VSB
0
0
0
Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.
Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit.
Select output polarity of RSTOUT# (1: high active, 0: low active) by setting
this bit.
2
WD_HACTIVE
R/W 5VSB
0
Select output pulse width of RSTOUT#
1-0
WD_PSWIDTH
R/W 5VSB
0
0: 1 ms
2: 125 ms
1: 25 ms
3: 5 sec
7.8.5Watchdog Timer Configuration Register 2 ⎯ Index F6h
Bit
Name
R/W Reset Default
Description
Description
Time of watchdog timer (0~255)
7-0
WD_TIME
R/W 5VSB
0
7.8.6Watchdog PME Enable Configuration Register 2 ⎯ Index FAh
Bit
Name
R/W Reset Default
0: No WDT PME occurred.
1: WDT PME occurred.
7
WDT_PME
R
5VSB
0
The WDT PME is occurred one unit before WDT timeout.
0: Disable Watchdog PME.
1: enable Watchdog PME.
6
5
WDT_PME_EN
Reserved
R/W 5VSB
0
0
Reserved
R
-
WDT Clock Source Select
0: Internal 1KHz clock.
1: 1KHZ clock driven by CLKIN.
Reserved
4
WDT_CLK_SEL
R/W 5VSB
1
3-1
0
Reserved
R
-
0
0
0: disable Watchdog time out output via WDTRST#.
1: enable Watchdog time out output via WDTRST#.
WDOUT_EN
R/W 5VSB
167
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
