F81866A
0: Data received has no parity error.
1: Data received has parity error.
0: No overrun condition occurred.
1: An overrun condition occurred.
0: No data is ready for read.
1: Data is received.
2
1
0
PE
OE
DR
R
R
R
LRESET#
LRESET#
LRESET#
0
0
0
MODEM Status Register (MSR) ⎯ Base + 6
Bit
Name
R/W Reset Default
Description
Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2
in MCR.
7
DCD
R
R
R
R
R
R
R
R
-
-
-
Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in
MCR
6
5
4
3
2
1
0
RI
-
Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in
MCR
DSR
-
-
Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in
MCR
CTS
-
-
0: No state changed at DCD#.
1: State changed at DCD#.
0: No Trailing edge at RI#.
1: A low to high transition at RI#.
0: No state changed at DSR#.
1: State changed at DSR#.
0: No state changed at CTS#.
1: State changed at CTS#.
DDCD
TERI
DDSR
DCTS
LRESET#
LRESET#
LRESET#
LRESET#
0
0
1
1
Scratch Register ⎯ Base + 7
Bit
Name
R/W Reset Default
R/W LRESET# 00h Scratch register.
Description
7-0
SCR
112
Jan, 2012
V0. 12P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
