F81218
1:0
SELURCCLK1
SELURCCLK0
R/W
00 : UART 3 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
6.8 Address Decoder 0 Device Control Register (LDN 6)
6.8.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x00h.
Bit
7:1
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
0
ADDEC0_EN
0 : Disable Address Decoder 0.
1 : Enable Address Decoder 0.
6.8.2 Address Decoder Select Register 0– index 60h
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
R/W
Description
DEC0_BASE[15:8]
R/W
Address high byte for ADD_DEC0/LPC_DEC0 .
6.8.3 Address Decoder Select Register 1– index 61h
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
R/W
Description
DEC0_BASE[7:0] R/W
Address low byte for ADD_DEC0/LPC_DEC0.
6.8.4 Address Mask Register – index 62h
Power-on default [7:0] = 0x00h
Bit
7:3
2:0
Name
Reserved
DEC0_SEL[2:0]
R/W
R/W
R/W
Description
Return 0 when read.
000 : Decode all 16 bits .
001 : Decode bit 15:1
010 : Decode bit 15:2
011 : Decode bit 15:3
100 : Decode bit 15:4
-38-
August, 2007
V0.33P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
