F81216
7:0
URB_BASE[15:8] R/W
UART 2 I/O Port Address high byte.
6.3.3 I/O Port Select Register – index 61h
Power-on default [7:0] = 0xF8h when SOUT2/PS_2F8_IRQB is pull-up,
0xE0h when DTR2#/PS_2E0_IRQB is pull-up, else 0x00h.
Bit
7:0
Name
R/W
Description
UART 2 I/O Port Address low byte.
URB_BASE[7:0]
R/W
6.3.4 IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x03h when SOUT2/PS_2F8_IRQB or DTR2#/PS_2E0_IRQB is pull-up,
else 0x00h
Bit
7:6
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
5
URBIRQ_MODE
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
Select the Serial IRQ channel.
4
URBIRQ_SHAR
R/W
3:0
SELURAIRQ[3:0] R/W
6.3.5 UART 2 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
7:2
1:0
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
SELURACLK1
SELURACLK0
00 : UART 2 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
6.4 UART 3 Device Control Register (LDN 2)
-23-
August, 2007
V0.32P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
