F81216
Bit
7:0
Name
VENDID
R/W
Description
R
Return 1934h when read index 23h and 24h respectively, indicate the
vendor ID of Fintek.
6.1.5 Clock Source Select Register – index 25h
Power-on default [7:0], 0x00h
Bit
7:1
Name
Reserved
CLK_SEL
R/W
R/W
R/W
Description
Return 0 when read.
0
1 : The CLKIN is 48MHz
0 : The CLKIN is 24MHz.
This bit must program to indicate the frequency of the clock source, or
the device will not function correctly.
6.1.6 Test Mode Register – index 2Fh
Power-on default [7:0], 0000_0000b
Bit
7:0
Name
R/W
Description
TESTMODE
R/W
Test mode register, reserved for Fintek use only.
6.2 UART 1 Device Control Register (LDN 0)
6.2.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h.
Bit
7:1
Name
Reserved
URA_EN
R/W
R/W
R/W
Description
Return 0 when read.
0 : Disable UART 1.
1 : Enable UART 1..
0
6.2.2 I/O Port Select Register – index 60h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pullup,
else 0x00h.
Bit
Name
R/W
Description
-20-
August, 2007
V0.32P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
