F81216
6.4.5 UART 3 Clock Select Register – index F0h
Power-on default [7:0] = 0000_0000b.
Bit
7:2
1:0
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
SELURCCLK1
SELURCCLK0
00 : UART 3 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
6.5 UART 4 Device Control Register (LDN 3)
6.5.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
7:1
Name
Reserved
URD_EN
R/W
R/W
R/W
Description
Return 0 when read.
0 : Disable UART 4.
1 : Enable UART 4.
0
6.5.2 I/O Port Select Register – index 60h
Power-on default [7:0] = 0x02h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit Name R/W Description
7:0 URD_BASE[15:8] R/W UART 4 I/O Port Address high byte.
6.5.3 I/O Port Select Register – index 61h
Power-on default [7:0] = 0xE8h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
7:0
Name
R/W
Description
UART 4 I/O Port Address low byte.
URD_BASE[7:0]
R/W
-25-
August, 2007
V0.32P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
