F81216
6.5.4 IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x09h when SOUT4/PS_2E8_IRQD is pull-up, else 0x00h.
Bit
7:6
5
Name
Reserved
URDIRQ_MODE
R/W
Description
R/W
R/W
Return 0 when read.
0 : PCI IRQ sharing mode
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
4
URDIRQ_SHAR
R/W
3:0
SELURDIRQ[3:0] R/W
Select the Serial IRQ channel.
6.5.5 UART 4 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
7:2
1:0
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
SELURDCLK1
SELURDCLK0
00 : UART 4 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
6.6 Watch Dog Timer Device Control Register (LDN 8)
6.6.1 Device Enable Register – index 30h
Power-on default [7:0] = 0x01h when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
7:1
Name
Reserved
WDT_EN
R/W
R/W
R/W
Description
Return 0 when read.
0
0 : Disable Watchdog Timer.
1 : Enable Watchdog Timer.
6.6.2 I/O Port Select Register – index 60h
Power-on default [7:0] = 0x04h when DTR3#/PS_WDT is pull-up, else 0x00h.
Bit
7:0
Name
R/W
R/W
Description
WDT_BASE[15:8]
I/O Base high byte.
-26-
August, 2007
V0.32P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
