F81216
7:0
URA_BASE[15:8] R/W
UART 1 I/O Port Address high byte.
6.2.3 I/O Port Select Register – index 61h
Power-on default [7:0] = 0xF8h when SOUT1/PS_3F8_IRQA is pull-up,
0xE0h when DTR1#/PS_3E0_IRQA is pull-up, else 0x00h.
Bit
7:0
Name
R/W
Description
UART 1 I/O Port Address low byte.
URA_BASE[7:0]
R/W
6.2.4 IRQ Channel Select Register – index 70h
Power-on default [7:0] = 0x03h when SOUT1/PS_3F8_IRQA or DTR1#/PS_3E0_IRQA is pull-up,
else 0x00h
Bit
7:6
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
5
URAIRQ_MODE
0 : PCI IRQ sharing mode.
1 : ISA IRQ sharing mode.
This bit is effective in IRQ sharing mode.
0 : IRQ is not sharing with other device.
1 : IRQ is sharing with other device.
Select the Serial IRQ channel.
4
URAIRQ_SHAR
R/W
3:0
SELURAIRQ[3:0] R/W
6.2.5 UART 1 Clock Select Register – index F0h
Power-on default [7:0] = 0x00h.
Bit
7:4
Name
Reserved
R/W
R/W
R/W
Description
Return 0 when read.
3
RXW4C_IRA
0 : No reception delay when SIR is changed from TX to RX.
1 : Reception delay 4 character-time when SIR is changed from TX
to RX.
2
TXW4C_IRA
R/W
R/W
0 : No transmission delay when SIR is changed from RX to TX.
1 : Transmission delay 4 character-time when SIR is changed from
RX to TX.
1:0
SELURACLK1
SELURACLK0
00 : UART 1 clock source is 1.8462MHz ( 24MHz/13 )
01/10/11 selection reserved.
-21-
August, 2007
V0.32P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
