F81216
OUT1 in MCR
5
4
3
DSR
R
R
R
Complement of DSR# input. In loop back mode , this bit is
equivalent to DTR in MCR
CTS
Complement of CTS# input. In loop back mode , this bit is equivalent
to RTS in MCR
DDCD
0 : No state changed at DCD#.
1 : State changed at DCD#.
2
1
0
TERI
R
R
R
0 : No Trailing edge at RI#.
1 : A low to high transition at RI#.
0 : No state changed at DSR#.
1 : State changed at DSR#.
0 : No state changed at CTS#.
1 : State changed at CTS#.
DDSR
DCTS
5.2.1.11 Scratch Register – Base + 7
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
R/W
Description
SCR_DATA[7:0]
R/W
Scratch register.
5.3 IR Function
The F81216 infrared interface provides a two way wireless communications port using
infrared as the transmission medium. The IrDA 1.0 (SIR) is found in UART1 IrDA SIR specifies
asynchronous serial communication at baud rate up to 115.2Kbps. Each byte is sent serial LSB first
beginning with a zero value start bit. A zero is signaled by sending a single infrared pulse at the
beginning of the serial bit time. A one is signaled by the absence of an infrared pulse during the bit
time. IRTX acts as a transmit pin and IRRX acts as a receiving one. As for detail description, please
refer to register description.
5.4 Watch Dog Timer Function
Watch dog timer is provided for system controlling. If time-out can trigger one signal to low
level, the signal default is tri-state (need external pull up resister).
The time interval has three ways:
One is the hardware power on setting to enable, timer set to 10 second (24MHz). If 48MHz
clock input, the timer is set to 5 second.
-13-
August, 2007
V0.32P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
