F81216
5.2.1.5 Interrupt Enable Register – Base + 1
Power-on default [7:0] = 0x00h.
Bit
7:4
Name
Reserved
R/W
R/W
R/W
R/W
R/W
Description
Return 0 when read. Access only when LCR[7] is 0
3
2
1
EDSSI
ELSI
Enable Modem Status Interrupt. Access only when LCR[7] is 0.
Enable Line Status Error Interrupt. Access only when LCR[7] is 0.
Enable Transmitter Holding Register Empty Interrupt. Access only
when LCR[7] is 0.
ETBFI
0
ERBFI
R/W
Enable Received Data Available Interrupt. Access only when LCR[7]
is 0
5.2.1.6 Interrupt Identification Register – Base + 2
Power-on default [7:0] = 0x01h.
Bit
Name
FIFO_EN
R/W
Description
7
R
0 : FIFO is disabled
1 : FIFO is enabled.
0 : FIFO is disabled.
1 : FIFO is enabled.
Return 0 when read.
6
FIFO_EN
R
5:4
3:1
Reserved
R
R
IRQ_ID[2:0]
000 : Interrupt is caused by Modem Status
001 : Interrupt is caused by Transmitter Holding Register Empty
010 : Interrupt is caused by Received Data Available.
110 : Interrupt is caused by Character Timeout
011 : Interrupt is caused by Line Status..
1 : Interrupt is not pending.
0
IRQ_PENDN
R
0 : Interrupt is pending.
5.2.1.7 FIFO Control Register – Base + 2
Power-on default [7:0] = 0x00h.
Bit
7:6
Name
R/W
Description
00 : Receiver FIFO trigger level is 1.
RCVR_TRIG[1:0]
W
01 : Receiver FIFO trigger level is 4.
10 : Receiver FIFO trigger level is 8.
-10-
August, 2007
V0.32P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
