F81216
transmission are baud rate, number of information bits per character, type of parity checking,
number of stop bits and breaking the transmission. The serial format is a start bit, followed by
five to eight data bits, a parity bit(if programmable), and one, one and half, or two stop bits. The
UART also includes completed modem control capability and interrupt system that may be
software trailed to the computing time required to handle the communication link. The UART
also has a FIFO mode to reduce the number of interrupts presented to the CPU. In the UART,
there is 16-byte FIFO for both receive and transmit mode.
5.2.1 UART Port Register
5.2.1.1 Receiver Buffer Register – Base + 0
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
RBR[7:0]
R/W
Description
R
The data received .
Read only when LCR[7] is 0
5.2.1.2 Transmitter Holding Register – Base + 0
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
THR[7:0]
R/W
Description
W
Data to be transmitted.
Write only when LCR[7] is 0
5.2.1.3 Divisor Latch ( LS ) – Base + 0
Power-on default [7:0] = 0x01h.
Bit
7:0
Name
DLL[7:0]
R/W
Description
Baud generator divisor low byte.
Access only when LCR[7] is 1.
R/W
5.2.1.4 Divisor Latch ( MS ) – Base + 1
Power-on default [7:0] = 0x00h.
Bit
7:0
Name
DLM[7:0]
R/W
Description
Baud generator divisor high byte.
R/W
Access only when LCR[7] is 1.
-9-
August, 2007
V0.32P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
