Feature Integration Technology Inc.
Fintek
F75373
4
3
2
1
0
VT1EXC
V3EXC
V2EXC
V1EXC
VCCEXC
R/W
R/W
R/W
R/W
R/W
A one indicates a high limit of VT1 has been exceeded. A zero
indicates VT1 is below the hysteresis limit.
A one indicates a high or low limit of VIN3 has been exceeded. A zero
indicates VIN3 is in the safe region.
A one indicates a high or low limit of VIN2 has been exceeded. . A
zero indicates VIN2 is in the safe region.
A one indicates a high or low limit of VIN1 has been exceeded. . A
zero indicates VIN1 is in the safe region.
A one indicates a high or low limit of VCC has been exceeded. . A
zero indicates VCC is in the safe region.
6.10
IRQ/SMI# ENABLE Register 2 Index 33h
Power on default: 00h
Bit
7-2
1
Name
Attribute
RO
Description
Reserved
EN_TARF2_SMI
R/W
Target fan2 SMI enable bit. A zero disables the corresponding
interrupt status bit for SMI# interrupt
0
EN_TARF1_SMI
R/W
Target fan1 SMI enable bit. A zero disables the corresponding
interrupt status bit for SMI# interrupt
6.11
Interrupt Status Register 2 Index 34h
Power on default: 00h
Bit
7-2
Name
Reserved
Attribute
Description
1
STS_TAR_FAN2
R/W A one indicates fan2 reading count is over then fan2 expect count,
and the PWMOUT2 duty cycle is full more then the FAN FAULT
TIME. Write 1 to clear this bit, write 0 will be ignored.
0
STS_TAR_FAN1
R/W
A one indicates fan1 reading count is over then fan1 expect count,
and the PWMOUT1 duty cycle is full more then the FAN FAULT
TIME. Write 1 to clear this bit, write 0 will be ignored.
19
V0.25P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
