7
RST_ENABLE
WD1_PTIME
R/W
R/W
VSB3V
VSB3V
Enable RESET Output Timer. If set to 1, the RSTOUT timer will be
started. When RSTOUT# is asserted, low pulse is occurred, the VID
will re-latched and disable EN_VIDOUT. The status of Reset Out is
stored in CR02.b1.
6-0
RSTOUT Pre-counter time in second.
000_0000b – 0 second (Default)
000_0001b – 1 second
000_0010b – 2 seconds
:
111_1111b – 127 seconds
7.42 Watchdog Timer Control Register – Index 36h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
Reserved
RO
VSB3V Reserved. Read will return 0.
6
STS_WD_TMO R/W
UT
VSB3V Watchdog is timeout. When the watchdog is timeout, this bit will be set to
one. If set to 1, write 1 will clear this bit. Write 0, no effect.
VSB3V Enable watchdog timer.
5
4
WD_ENABLE
WD_PULSE
R/W
R/W
VSB3V Watchdog output level or pulse. If set 0 (default), the pin of watchdog is
level output. If write 1, the pin will output with a pulse.
VSB3V Watchdog unit select. Default 0 is select second. Write 1 to select minute.
VSB3V Program WD output level. If set to 1 and watchdog asserted, the pin will be
high. If set to 0 and watchdog asserted, this pin will drive low(default).
VSB3V Watchdog pulse width selection. If the pin output is selected to pulse mode.
The pulse width can be choice.
3
2
WD_UNIT
R/W
R/W
WD_HACTIVE
1-0
WD_PSWIDTH R/W
00b – 1m second.
01b – 20m second.
10b – 100m second
11b – 4 second
The is flexible reset out with watchdog
7.43 Watchdog Timer Range Register – Index 37h
Power-on default [7:0] =0000_0000b
- 32 -
July, 2007
V0.24P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
