0
EN_GP30EDGE
R/W
VSB3V Enable GPIO30 Edge Detector. If set to 1, enable GPIO30 edge detection.
Default is disable.
7.52 Edge Detector Status Register – Index 0x49
Power-on default [7:0] =0000_0000b
Bit
7-4
3
Name
Reserved
R/W
PWR
Description
RO
VSB3V Read back will be zero
STS_GP33EDGE R/W
STS_GP32EDGE R/W
STS_GP31EDGE R/W
STS_GP30EDGE R/W
VSB3V Indicate GPIO33 Edge Status. If set to 1, the edge of GPIO33 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
2
1
0
VSB3V Indicate GPIO32 Edge Status. If set to 1, the edge of GPIO32 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO31 Edge Status. If set to 1, the edge of GPIO31 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO10 Edge Status. If set to 1, the edge of GPIO30 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
7.53 IRQ or SMI# Enable Register – Index 0x4A
Power-on default [7:0] =0000_0000b
Bit
7-4
3
Name
Reserved
R/W
RO
PWR
Description
VSB3V Read back will be zero
EN_GP33IRQ
R/W
VSB3V Enable GPIO33 IRQ or SMI# Generation. If this bit set to 1, enable GPIO33
to generate IRQ or SMI#.
2
1
0
EN_GP32IRQ
EN_GP31IRQ
EN_GP30IRQ
R/W
R/W
R/W
VSB3V Enable GPIO32 IRQ or SMI# Generation. If this bit set to 1, enable GPIO32
to generate IRQ or SMI#.
VSB3V Enable GPIO31 IRQ or SMI# Generation. If this bit set to 1, enable GPIO31
to generate IRQ or SMI#.
VSB3V Enable GPIO30 IRQ or SMI# Generation. If this bit set to 1, enable GPIO30
- 36 -
July, 2007
V0.24P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
