0
GP30_PSTS
RO
VSB3V Read the GPIO30 data on the pin.
7.47 GPIO3x Level/Pulse Control Register – Index 43h
Power-on default [7:0] =0000_0000b
Bit
7-4
3
Name
R/W
PWR
Description
Reserved
RO
VSB3V Read back will be zero
GP33_OMODE R/W
GP32_OMODE R/W
GP31_OMODE R/W
GP37_OMODE R/W
VSB3V GPIO 33 output mode. 0 – level, 1 – pulse.
VSB3V GPIO 32 output mode. 0 – level, 1 – pulse.
VSB3V GPIO 31 output mode. 0 – level, 1 – pulse.
VSB3V GPIO 30 output mode. 0 – level, 1 – pulse.
2
1
0
7.48 GPIO3x Pulse Width Control Register – Index 44h
Power-on default [7:0] =0000_0000b
Bit
7:2
1:0
Name
Reserved
R/W
PWR
Description
R/W
VSB3V Reserved. Read return 0.
GP3_PLSWD[1:0 R/W
]
VSB3V GPIO3x pulse width. If set the GPIO3x to pulse mode, the pulse width
can be defined as follows.
00b – 500us (Default)
01b – 1ms
10b – 20ms
11b – 100ms
7.49 GPIO3x Input De-bounce Register – Index 46h
Power-on default [7:0] =0000_0000b
Bit
7-4
3
Name
Reserved
R/W
RO
PWR
Description
VSB3V Read back will be zero
GP33_ENDB
R/W
VSB3V Enable GPIO33 input de-bounce with 7u or 25ms second that selected by
0x4C bit3.
- 34 -
July, 2007
V0.24P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
