2
1
0
STS_GP22EDGE R/W
STS_GP21EDGE R/W
STS_GP20EDGE R/W
VSB3V Indicate GPIO22 Edge Status. If set to 1, the edge of GPIO22 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO11 Edge Status. If set to 1, the edge of GPIO21 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO10 Edge Status. If set to 1, the edge of GPIO20 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
7.33 IRQ or SMI# Enable Register – Index 0x2A
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
EN_GP27IRQ
R/W
VSB3V Enable GPIO27 IRQ or SMI# Generation. If this bit set to 1, enable GPIO27
to generate IRQ or SMI#.
6
5
4
3
2
1
0
EN_GP26IRQ
EN_GP25IRQ
EN_GP24IRQ
EN_GP23IRQ
EN_GP22IRQ
EN_GP21IRQ
EN_GP20IRQ
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VSB3V Enable GPIO26 IRQ or SMI# Generation. If this bit set to 1, enable GPIO26
to generate IRQ or SMI#.
VSB3V Enable GPIO25 IRQ or SMI# Generation. If this bit set to 1, enable GPIO25
to generate IRQ or SMI#.
VSB3V Enable GPIO24 IRQ or SMI# Generation. If this bit set to 1, enable GPIO24
to generate IRQ or SMI#.
VSB3V Enable GPIO23 IRQ or SMI# Generation. If this bit set to 1, enable GPIO23
to generate IRQ or SMI#.
VSB3V Enable GPIO22 IRQ or SMI# Generation. If this bit set to 1, enable GPIO22
to generate IRQ or SMI#.
VSB3V Enable GPIO21 IRQ or SMI# Generation. If this bit set to 1, enable GPIO21
to generate IRQ or SMI#.
VSB3V Enable GPIO20 IRQ or SMI# Generation. If this bit set to 1, enable GPIO20
to generate IRQ or SMI#.
- 28 -
July, 2007
V0.24P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
