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F75111R 参数 Datasheet PDF下载

F75111R图片预览
型号: F75111R
PDF下载: 下载PDF文件 查看货源
内容描述: 低功耗GPIO数据表 [Low Power GPIO Datasheet]
分类和应用:
文件页数/大小: 45 页 / 967 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F75111  
25ms else if set to 0 de-bounce time is 7u(default).  
6
5
4
3
2
1
0
DB_TIME26_SEL R/W  
DB_TIME25_SEL R/W  
DB_TIME24_SEL R/W  
DB_TIME23_SEL R/W  
DB_TIME22_SEL R/W  
DB_TIME21_SEL R/W  
DB_TIME20_SEL R/W  
VSB3V Select GPIO26 input de-bounce time. If set to 1 de-bounce time is  
25ms else if set to 0 de-bounce time is 7u(default).  
VSB3V Select GPIO25 input de-bounce time. If set to 1 de-bounce time is  
25ms else if set to 0 de-bounce time is 7u(default).  
VSB3V Select GPIO24 input de-bounce time. If set to 1 de-bounce time is  
25ms else if set to 0 de-bounce time is 7u(default).  
VSB3V Select GPIO23 input de-bounce time. If set to 1 de-bounce time is  
25ms else if set to 0 de-bounce time is 7u(default).  
VSB3V Select GPIO22 input de-bounce time. If set to 1 de-bounce time is  
25ms else if set to 0 de-bounce time is 7u(default).  
VSB3V Select GPIO21 input de-bounce time. If set to 1 de-bounce time is  
25ms else if set to 0 de-bounce time is 7u(default).  
VSB3V Select GPIO20 input de-bounce time. If set to 1 de-bounce time is  
25ms else if set to 0 de-bounce time is 7u(default).  
7.36 WDTOUT Control Register – Index 34h  
Power-on default [7:0] =0000_0000b  
Bit  
7-3  
2
Name  
Reserved  
SEL_RST_2S  
R/W  
RO  
PWR  
VSB3V  
VSB3V  
VSB3V  
Description  
R/W  
When set this bit to 1, the WDTOUT10 low pulse width is 2 Sec, if set  
to 0 the low pulse width is 100ms.  
1
0
WDTOUT10_OIN R/W  
V
WDTOUT10# output level inverting. When write 1, the output pin will  
be inverted. Default is low active when time is out.  
Indicate WDTOUT10 is occurred. Write 1 to clear this bit. Writing 0 is  
invalid.  
STS_WDTOUT1  
0
R/W  
7.37 WDTOUT10 Control Register – Index 35h  
Power-on default [7:0] =0000_0000b  
Bit  
Name  
R/W  
PWR  
Description  
Enable WDTOUT10 Output Timer. If set to 1, the WDTOUT10 timer  
will be started. When WDTOUT10# is asserted, low pulse is  
occurred.  
7
WDT10_ENABLE R/W  
VSB3V  
- 30 -  
July, 2007  
V0.27P  
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