F75111
disabled.
7.32 GP2X Edge Detector Status Register – Index 0x29
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
STS_GP27EDGE R/W
STS_GP26EDGE R/W
STS_GP25EDGE R/W
STS_GP24EDGE R/W
STS_GP23EDGE R/W
STS_GP22EDGE R/W
STS_GP21EDGE R/W
STS_GP20EDGE R/W
VSB3V Indicate GPIO27 Edge Status. If set to 1, the edge of GPIO27 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
6
5
4
3
2
1
0
VSB3V Indicate GPIO26 Edge Status. If set to 1, the edge of GPIO26 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO25 Edge Status. If set to 1, the edge of GPIO25 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO24 Edge Status. If set to 1, the edge of GPIO24 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO23 Edge Status. If set to 1, the edge of GPIO23 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO22 Edge Status. If set to 1, the edge of GPIO22 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO11 Edge Status. If set to 1, the edge of GPIO21 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
VSB3V Indicate GPIO10 Edge Status. If set to 1, the edge of GPIO20 has
occurred. Write 1 to clear this bit. Writing 0 is invalid.
7.33 GP2X IRQ or SMI# Enable Register – Index 0x2A
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
EN_GP27IRQ
R/W
VSB3V Enable GPIO27 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO27 to generate IRQ or SMI#.
6
5
4
EN_GP26IRQ
EN_GP25IRQ
EN_GP24IRQ
R/W
R/W
R/W
VSB3V Enable GPIO26 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO26 to generate IRQ or SMI#.
VSB3V Enable GPIO25 IRQ or SMI# Generation. If this bit set to 1, enable
GPIO25 to generate IRQ or SMI#.
VSB3V Enable GPIO24 IRQ or SMI# Generation. If this bit set to 1, enable
- 28 -
July, 2007
V0.27P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
