F75111
7.46 GPIO3x Pulse Inverse Register – Index 47h
Power-on default [7:0] =0000_0000b
Bit
7-4
3
Name
Reserved
R/W
RO
PWR
Description
VSB3V Read back will be zero
GP33_PULSINV
GP32_PULSINV
GP31_PULSINV
GP30_PULSINV
R/W
R/W
R/W
R/W
VSB3V GPIO33 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR44.
2
1
0
VSB3V GPIO32 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR44.
VSB3V GPIO 31 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR44.
VSB3V GPIO30 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR44.
7.47 GP3x Edge Detector Enable Register – Index 0x48
Power-on default [7:0] =0000_0000b
Bit
7-4
3
Name
Reserved
R/W
RO
PWR
Description
VSB3V Read back will be zero
EN_GP33EDGE
EN_GP32EDGE
EN_GP31EDGE
EN_GP30EDGE
R/W
VSB3V Enable GPIO33 Edge Detector. If set to 1, enable GPIO33 edge
detection. Default is disable.
2
1
0
R/W
R/W
R/W
VSB3V Enable GPIO32 Edge Detector. If set to 1, enable GPIO32 edge
detection. Default is disable.
VSB3V Enable GPIO31 Edge Detector. If set to 1, enable GPIO31 edge
detection. Default is disable.
VSB3V Enable GPIO30 Edge Detector. If set to 1, enable GPIO30 edge
detection. Default is disable.
7.48 GP3X Edge Detector Status Register – Index 0x49
Power-on default [7:0] =0000_0000b
- 34 -
July, 2007
V0.27P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
