F75111
CR24.
1
0
GP21_PULSINV
GP20_PULSINV
R/W
R/W
VSB3V GPIO 21 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR24.
VSB3V GPIO20 Pulse inversed. If the pulse inverse is selected, the output
pulse is high pulse. Default low pulse. The pulse width is defined in
CR24.
7.31 GP2x Edge Detector Enable Register – Index 0x28
Power-on default [7:0] =0000_0000b
Bit
Name
R/W
PWR
Description
7
EN_GP27EDGE
R/W
VSB3V Enable GPIO27 Edge Detector. If this bit set to 1 and GPIO17 set to
input mode [CR10] will enable GPIO27 edge detection. Default is
disabled.
6
5
4
3
2
1
0
EN_GP26EDGE
EN_GP25EDGE
EN_GP24EDGE
EN_GP23EDGE
EN_GP22EDGE
EN_GP21EDGE
EN_GP20EDGE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VSB3V Enable GPIO26 Edge Detector. If this bit set to 1 and GPIO16 set to
input mode [CR10] will enable GPIO26 edge detection. Default is
disabled.
VSB3V Enable GPIO25 Edge Detector. If this bit set to 1 and GPIO15 set to
input mode [CR10] will enable GPIO25 edge detection. Default is
disabled.
VSB3V Enable GPIO24 Edge Detector. If this bit set to 1 and GPIO14 set to
input mode [CR10] will enable GPIO24 edge detection. Default is
disabled.
VSB3V Enable GPIO23 Edge Detector. If this bit set to 1 and GPIO13 set to
input mode [CR10] will enable GPIO23 edge detection. Default is
disabled.
VSB3V Enable GPIO22 Edge Detector. If this bit set to 1 and GPIO12 set to
input mode [CR10] will enable GPIO22 edge detection. Default is
disabled.
VSB3V Enable GPIO21 Edge Detector. If this bit set to 1 and GPIO11 set to
input mode [CR10] will enable GPIO21 edge detection. Default is
disabled.
VSB3V Enable GPIO20 Edge Detector. If this bit set to 1 and GPIO10 set to
input mode [CR10] will enable GPIO20 edge detection. Default is
- 27 -
July, 2007
V0.27P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
