F71872
0: No overrun condition occurred.
1: An overrun condition occurred.
0: No data is ready for read.
1: Data is received.
1
0
OE
DR
R
R
0
0
7.3.3.11 MODEM Status Register Base + 6
Bit
Name
R/W Default
Description
Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2
7
DCD
RI
R
R
R
R
R
R
R
R
-
in MCR.
Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in
MCR
Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in
MCR
Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in
MCR
0: No state changed at DCD#.
1: State changed at DCD#.
0: No Trailing edge at RI#.
1: A low to high transition at RI#.
0: No state changed at DSR#.
1: State changed at DSR#.
0: No state changed at CTS#.
1: State changed at CTS#.
6
5
4
3
2
1
0
-
DSR
CTS
-
-
DDCD
TERI
DDSR
DCTS
0
0
0
0
7.3.3.12 Scratch Register Base + 7
Bit
Name
R/W Default
Description
Scratch register.
7-0 SCR
R/W
00h
7.4 UART 2 Registers
7.4.1 Logic Device Number Register
Logic Device Number Register Index 07H
Bit
Name
R/W Default
Description
56
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
