F71872
7.3.3.3 Divisor Latch (LSB) Base + 0
Bit
Name
R/W Default
Description
Description
Description
Baud generator divisor low byte.
Access only when LCR[7] is 1.
7-0 DLL
R/W
01h
7.3.3.4 Divisor Latch (MSB) Base + 1
Bit
Name
R/W Default
Baud generator divisor high byte.
Access only when LCR[7] is 1.
7-0 DLM
R/W
00h
7.3.3.5 Interrupt Enable Register Base + 1
Bit
Name
R/W Default
7-4 Reserved
-
-
Reserved.
Enable Modem Status Interrupt. Access only when LCR[7] is 0.
3
2
1
EDSSI
ELSI
R/W
R/W
R/W
0
0
0
Enable Line Status Error Interrupt. Access only when LCR[7] is 0.
ETBFI
Enable Transmitter Holding Register Empty Interrupt. Access only when
LCR[7] is 0.
0
ERBFI
R/W
0
Enable Received Data Available Interrupt. Access only when LCR[7] is 0.
7.3.3.6 Interrupt Identification Register Base + 2
Bit
Name
FIFO_EN
R/W Default
Description
0: FIFO is disabled
1: FIFO is enabled.
0: FIFO is disabled
1: FIFO is enabled.
7
R
0
6
FIFO_EN
R
0
5-4 Reserved
3-1 IRQ_ID
-
-
Reserved.
000: Interrupt is caused by Modem Status
R
000
001: Interrupt is caused by Transmitter Holding Register Empty
010: Interrupt is caused by Received Data Available.
110: Interrupt is caused by Character Timeout
011: Interrupt is caused by Line Status.
1: Interrupt is not pending.
0: Interrupt is pending.
0
IRQ_PENDN
R
1
7.3.3.7 FIFO Control Register Base + 2
Bit
Name
R/W Default
Description
00: Receiver FIFO trigger level is 1.
01: Receiver FIFO trigger level is 4.
10: Receiver FIFO trigger level is 8.
7-6 RCV_TRIG
W
00
11: Receiver FIFO trigger level is 14.
5-3 Reserved
-
-
Reserved.
Reset the transmitter FIFO.
2
1
CLRTX
CLRRX
R
R
0
0
Reset the receiver FIFO.
54
July, 2007
V0.28P