F71872
0: Disable FIFO.
1: Enable FIFO.
0
FIFO_EN
R
0
7.3.3.8 Line Control Register Base + 3
Bit
Name
R/W Default
Description
0: Divisor Latch can’t be accessed.
7
DLAB
R/W
0
1: Divisor Latch can be accessed via Base and Base+1.
0: Transmitter is in normal condition.
1: Transmit a break condition.
XX0: Parity Bit is disable
6
SETBRK
R/W
0
5
4
3
STKPAR
EPS
R/W
R/W
R/W
0
0
0
001: Parity Bit is odd.
011: Parity Bit is even
PEN
101: Parity Bit is logic 1
111: Parity Bit is logic 0
0: Stop bit is one bit
1: When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
2
STB
R/W
R/W
0
00: Word length is 5 bit
1-0 WLS
00
01: Word length is 6 bit
10: Word length is 7 bit
11: Word length is 8 bit
7.3.3.9 MODEM Control Register Base + 4
Bit
Name
R/W Default
Description
Reserved.
7-5 Reserved
-
-
0: UART in normal condition.
1: UART is internal loop back
0: All interrupt is disabled.
4
3
LOOP
OUT2
R/W
0
R/W
0
1: Interrupt is enabled
(disabled) by IER.
Read from MSR[6] is loop back mode
2
1
OUT1
RTS
R/W
R/W
0
0
0: RTS# is forced to logic 1
1: RTS# is forced to logic 0
0: DTR# is forced to logic 1
1: DTR# is forced to logic 0
0
DTR
R/W
0
7.3.3.10 Line Status Register Base + 5
Bit
Name
RCR_ERR
R/W Default
Description
0: No error in the FIFO when FIFO is enabled
1: Error in the FIFO when FIFO is enabled.
0: Transmitter is in transmitting.
7
R
R
R
R
R
R
0
1
1
0
0
0
6
5
4
3
2
TEMT
THRE
BI
1: Transmitter is empty.
0: Transmitter Holding Register is not empty.
1: Transmitter Holding Register is empty.
0: No break condition detected.
1: A break condition is detected.
0: Data received has no frame error.
1: Data received has frame error.
0: Data received has no parity error.
1: Data received has parity error.
FE
PE
55
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
