F71872
4-2 PRECOMP
W
000 Select the value of write precompensation:
250K-1Mbps
000: default delays
001: 41.67ns
2Mbps
default delays
20.8ns
010: 83.34ns
41.17ns
011: 125.00ns
62.5ns
100: 166.67ns
83.3ns
101: 208.33ns
104.2ns
110: 250.00ns
111: 0.00ns (disabled)
125.00ns
0.00ns (disabled)
The default value of corresponding data rate:
250Kbps: 125ns
300Kbps: 125ns
500Kbps: 125ns
1Mbps: 41.67ns
2Mbps: 20.8ns
1-0 DRATE
W
10
Data rate select:
MFM
FM
00: 500Kbps
01: 300Kbps
10: 250Kbps
11: 1Mbps
250Kbps
150Kbps
125Kbps
illegal
7.2.3.9 Data (FIFO) Register Base + 5
Bit
Name
R/W Default
Description
7-0 DATA
R/W
00h The FIFO is used to transfer all commands, data and status between controller
and the system. The Data Register consists of four status registers in a stack
with only one register presented to the data bus at a time. The FIFO is default
disabled and could be enabled via the CONFIGURE command.
Status Registers 0
Bit
Name
R/W Default
Description
7-6 IC
R
-
Interrupt code :
00: Normal termination of command.
01: Abnormal termination of command.
10: Invalid command.
11: Abnormal termination caused by poling.
5
4
SE
EC
R
R
-
-
Seek end.
Set when a SEEK or RECALIBRATE or a READ or WRITE with implied seek
command is completed.
Equipment check.
0: No error
1: When a fault signal is received form the FDD or the TRK0# signal fails to
occur after 77 step pulses.
40
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
