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F71872FG 参数 Datasheet PDF下载

F71872FG图片预览
型号: F71872FG
PDF下载: 下载PDF文件 查看货源
内容描述: 超级H / W监控+ LPC IO [Super H/W Monitor + LPC IO]
分类和应用: 监控PC
文件页数/大小: 115 页 / 3055 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71872  
EC  
EOT  
EFIFO  
Enable Count  
End of Track  
Enable FIFO  
0: FIFO is enabled.  
1: FIFO is disabled.  
EIS  
FIFOTHR  
GAP  
GPL  
H/HDS  
HLT  
HUT  
LOCK  
Enable Implied Seek  
FIFO Threshold  
Alters Gap Length  
Gap Length  
Head Address  
Head Load Time  
Head Unload Time  
Lock EFIFO, FIFOTHR, PTRTRK bits.  
Prevent these bits from being affected by software reset.  
MFM  
MFM or FM mode  
0: FM  
1: MFM  
MT  
N
Multi-Track  
Sector Size Code. All values up to 07h are allowable.  
00:  
01:  
..  
128 bytes  
256 bytes  
..  
07  
16 Kbytes  
NCN  
ND  
OW  
New Cylinder Number  
Non-DMA Mode  
Overwritten  
PCN  
POLL  
Present Cylinder Number  
Polling disable  
0: polling is enabled.  
1: polling is disabled.  
Precompensation Start Track Number  
Sector address  
PRETRK  
R
RCN  
SC  
Relative Cylinder Number  
Sector per Cylinder  
Skip deleted data address mark  
Step Rate Time  
SK  
SRT  
ST0  
Status Register 0  
ST1  
Status Register 1  
ST2  
Status Register 2  
ST3  
Status Register 3  
WGATE  
Write Gate alters timing of WE.  
Read Data  
Phase  
R/W  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Remark  
Command  
W
MT  
MFM  
SK  
0
0
1
1
0
Command code  
W
W
W
W
0
0
0
0
0
HDS  
DS1  
DS0  
----------------------------- C ---------------------------  
----------------------------- H ---------------------------  
----------------------------- R ---------------------------  
Sector ID information  
prior to command  
execution  
44  
July, 2007  
V0.28P  
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