F71872
7.2.3.3 Status Register B (PS/2 Mode) Base + 1
Bit
Name
R/W Default
Description
7-6 Reserved
R
R
R
R
R
R
11
0
Reserved. Return 11b when read.
5
4
3
2
1
DR0
Drive select 0. This bit reflects the bit 0 of Digital Output Register.
This bit changes state at every rising edge of WDATA#.
This bit changes state at every rising edge of RDATA#.
WDATA
RDATA
WGATE
MOTEN1
0
0
0
This bit indicates the complement of WGATE# disk interface output.
0
This bit indicates the complement of MOB# disk interface output. Not support
in this design.
0
MOTEN0
R
0
This bit indicates the complement of MOA# disk interface output.
7.2.3.4 Status Register B (Model 30 Mode) Base + 1
Bit
Name
R/W Default
Description
7
DRV2_N
R
R
-
0: a second drive has been installed.
1: a second drive has not been installed.
6
DSB_N
1
This bit indicates the state of DRVB# disk interface output. Not support in this
design.
5
4
DSA_N
R
R
1
0
This bit indicates the state of DRVA# disk interface output.
WDATA_FF
This bit is latched at the rising edge of WDATA# and is cleared by a read from
the Digital Input Register.
3
2
1
0
RDATA_FF
WGATE_FF
DSD_N
R
R
R
R
0
0
1
1
This bit is latched at the rising edge of RDATA# and is cleared by a read form
the Digital Input Register.
This bit is latched at the falling edge of WGATE# and is cleared by a read from
the Digital Input Register.
This bit indicates the complement of DRVD# disk interface output. Not support
in this design.
DSC_N
This bit indicates the complement of DRVC# disk interface output. Not support
in this design.
7.2.3.5 Digital Output Register Base + 2
Bit
Name
R/W Default
Description
7
6
5
4
3
MOTEN3
R
0
0
0
0
0
Motor enable 3. Not support in this design.
MOTEN2
MOTEN1
MOTEN0
DAMEN
R
Motor enable 2. Not support in this design.
R/W
R/W
R/W
Motor enable 1. Used to control MOB#. MOB# is not support in this design.
Motor enable 0. Used to control MOA#.
DMA enable. This bit has two mode of operation.
PC-AT and Model 30 mode: write 1 will enable DMA and IRQ, write 0 will
disable DMA and IRQ.
PS/2 mode: This bit is reserved. DMA and IRQ are always enabled in PS/2
mode.
2
RESET
R
0
Write 0 to this bit will reset the controller. I will remain in reset condition until a 1
is written.
38
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
