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F71872FG 参数 Datasheet PDF下载

F71872FG图片预览
型号: F71872FG
PDF下载: 下载PDF文件 查看货源
内容描述: 超级H / W监控+ LPC IO [Super H/W Monitor + LPC IO]
分类和应用: 监控PC
文件页数/大小: 115 页 / 3055 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71872  
1
0
DSD_N  
DSC_N  
R
R
1
1
This bit indicates the complement of DRVD# disk interface output. Not support  
in this design.  
This bit indicates the complement of DRVC# disk interface output. Not support  
in this design.  
7.2.3.6 Tape Drive Register Base + 3  
Bit  
Name  
R/W Default  
Description  
7-6 Reserved  
5-4 TYPEID  
R
R
00  
11  
Reserved. Return 00b when read.  
Reserved in normal function, return 11b when read.  
If 3 mode FDD function is enabled. These bits indicate the drive type ID.  
3-2 Reserved  
1-0 TAPESEL  
R
11  
0
Reserved. Return 11b when read in normal function.  
Return 00b when read in 3 mode FDD function.  
R/W  
These bits assign a logical drive number to be a tape drive.  
7.2.3.7 Main Status Register Base + 4  
Bit  
Name  
R/W Default  
Description  
7
RQM  
DIO  
R
R
0
0
Request for Master indicates that the controller is ready to send or receive data  
from the uP through the FIFO.  
6
Data I/O (direction):  
0: the controller is expecting a byte to be written to the Data Register.  
1: the controller is expecting a byte to be read from the Data Register.  
5
NON_DMA  
R
0
Non DMA Mode:  
0: the controller is in DAM mode.  
1: the controller is interrupt or software polling mode.  
4
3
FDC_BUSY  
R
R
0
0
This bit indicate that a read or write command is in process.  
DRV3_BUSY  
FDD number 3 is in seek or calibration condition. FDD number 3 is not support  
in this design.  
2
1
0
DRV2_BUSY  
DRV1_BUSY  
DRV0_BUSY  
R
R
R
0
0
0
FDD number 2 is in seek or calibration condition. FDD number 2 is not support  
in this design.  
FDD number 1 is in seek or calibration condition. FDD number 1 is not support  
in this design.  
FDD number 0 is in seek or calibration condition.  
7.2.3.8 Data Rate Select Register Base + 4  
Bit  
Name  
R/W Default  
Description  
7
6
SOFTRST  
W
W
0
0
A 1 written to this bit will software reset the controller. Auto clear after reset.  
PWRDOWN  
Reserved  
A 1 to this bit will put the controller into low power mode which will turn off the  
oscillator and data separator circuits.  
5
-
-
Return 0 when read.  
39  
July, 2007  
V0.28P  
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