F71872
The below diagram described the timing, the always on and always off, keep last state could be set in
control register. In keep last state mode, one register will keep the status of before power loss. If it is power on
before power loss, it will remain power on when power is resumed, otherwise, if it is power off before power
loss, it will remain power off when power is resumed.
VBAT
VSB
RSM RST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
DEFAULT TIM ING
Alwaysoff
VBAT
VSB
RSM RST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
ALwaysON TIM ING
15
July, 2007
V0.28P