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F71872FG 参数 Datasheet PDF下载

F71872FG图片预览
型号: F71872FG
PDF下载: 下载PDF文件 查看货源
内容描述: 超级H / W监控+ LPC IO [Super H/W Monitor + LPC IO]
分类和应用: 监控PC
文件页数/大小: 115 页 / 3055 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71872  
36  
GPIO4/  
I/OOD12t VCC  
General purpose IO.  
Voltage_Fault2#/  
BEEP/  
1. Support Level and Pulse mode output.  
2. Open drain and drive select  
3. Without input de-bounce.  
VID_OTF#  
Voltage fault indication for VIN2 abnormal event.  
Beep Pin.  
Voltage OTF Enable pin. This Pin can be selected to be a  
input pin for VID_OTF enable.  
53  
55  
GPIO5/  
Voltage_Fault3#/  
FANCTL  
I/OOD12t VCC  
General purpose IO.  
1. Support Level and Pulse mode output.  
2. Open drain and drive select  
3. Without input de-bounce.  
Voltage fault indication for VIN3 abnormal event.  
Fan 1 control output for Intel 4-pin Fan. All the registers are  
as same as FANCTL1.  
General purpose IO.  
1. Support Level and Pulse mode output.  
2. Open drain and drive select  
3. Without input de-bounce.  
GPIO6/  
I/OOD12t VCC  
Voltage_Fault4#/  
WDTRST1#/  
OVT#  
Voltage fault indication for VIN4 abnormal event.  
Watch dog timer signal output 1.  
Over temperature signal output.  
77  
OVT#/  
GPIO24/  
WDTRST2#  
I/OOD12t VSB  
Over temperature signal output.(Default 85°C)  
General purpose IO. Open drain and drive select by register.  
Watch dog timer signal output 2.  
5.8 ACPI function pins  
Pin No. Pin Name  
Type  
PWR  
Description  
30  
RSTCON#/GPIO10 I/OD12t  
VCC  
RESET connect# with 50ms debouce function, it connects to  
reset button, and also other reset source on the  
motherboard. If the register RSTCON_EN (5h) is set to 1, the  
pin 30 will infect PCIRST1# ~ PCIRST5# outcome. If the  
register RSTCON_EN is set to 0, the pin 30 will infect  
PWROK1 and PWROK2 outcome.  
General purpose IO.  
31  
PCIRST1#/GPIO11 I/OOD16t VCC  
It is a output buffer of RSTCON# and LRESET#.  
General purpose IO.  
Pin1 RST_DRV = 1(high) : OD  
= 0(low) : Drive  
PWROK function, It is power good signal of VCC, which is  
delayed 400ms (default) as VCC arrives at 2.8V.  
General purpose IO.  
It is a output buffer of RSTCON# and LRESET#.  
General purpose IO.  
Pin1 RST_DRV = 1(high) : OD  
=0(low): Drive  
32  
33  
PWROK1/GPIO12  
I/OD12t  
VCC  
PCIRST2#/GPIO13 I/OOD16t VCC  
PCIRST3#/GPIO14 I/OOD16t VCC  
34  
It is a output buffer of RSTCON# and LRESET#.  
General purpose IO.  
12  
July, 2007  
V0.28P  
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