F71872
6.3 PCI Reset and PWROK Signals
The F71872 supports 5 output buffers for 5 reset signals. If the register RSTCON_EN (5h) is set to 1, the pin
RSTCON# will infect PCIRST1# ~ PCIRST5# outcome. Then, the result of PCIRST# outcome will be affected by
conditions as below:
PCIRST1# Æ Output buffer of RSTCON# and LRESET#.
PCIRST2# Æ Output buffer of RSTCON# and LRESET#.
PCIRST3# Æ Output buffer of RSTCON# and LRESET#.
PCIRST4# Æ Output buffer of RSTCON#, LRESET# and PCIRSTIN#
PCIRST5# Æ Output buffer of RSTCON#, LRESET# and PCIRSTIN#
+3.3V
RSTCON#
Delay
PCIRST1~3#
PCIRST4~5#
S3#
LRESET#
PW ROK1/2
ATXPG
RSTCON#
PCIRSTIN#
So far as the PWROK issue is as above figure. PWROK is delayed 400ms (default) as VCC arrives 2.8V,
and the delay timing can be programmed by register. (100ms ~ 400ms)
In the figure, the RSTCON# will be implemented by register RSTCON_EN. If RSTCON_EN be set to 0, the
RSTCON# pin will affect PWROK outputs. If RSTCON_EN be set to 1, the RSTCON# pin will affect PCIRST
outputs (Default).
6.4 Hardware Monitor
6.4.1 Analog Input
The F71872 provides 8 pins (8-bit) ADC voltage inputs. These input voltages should be positive and is
limited at range of 0v to 2.048V. The minimum resolution (1-LSB) is 8mV. If the voltage is over this range, the
divider resistor must be added and the divided voltage is also in the range of 0V to 2.048V.
The maximum input voltage of the analog pin is 2.048V because the 8-bit ADC has a 8mv LSB. Really, the
application of the PC monitoring would most often be connected to power suppliers. The voltage range of 0V to
2.048V can be connected to these analog inputs. The 3.3V and VSB5V should be reduced a factor with
external resistors so as to obtain the input range..
There are 8 voltage inputs in the F71872 and the voltage divided formula is shown as follows:
16
July, 2007
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
