F71862
8.10 SPI Registers (CR08)
8.10.1 Configuration Register
SPI Control Register Index F0h
Bit
Name
R/W Default
Description
7-6 Reserved
-
-
Reserved.
5
4
3
SPTIE
MSTR
CPOL
R/W
0
SPI interrupt enable. Set to 1, SPIE interrupt enabled, set to 0 spie interrupt
disabled.
R/W
R/W
1
0
Master mode select. Set to 1, SPI function is master mode; set to 0 is disable
SPI function
Clock polarity this bit selects inverted or non-inverted SPI clock. Set to 1, active
low clock selected; SCK idles high. Set to 0, active high clock selected; SCK
idles low.
2
CPHA
R/W
0
Clock phase. This bit is used to shift the SCK serial clock. Set to 1, the first
SCK edge is issued at the beginning of the transfer operation. Set to 0, the first
SCK edge is issued one-half cycle into the transfer operation.
1
0
Reserved
LSBFE
-
0
0
Reserved
R/W
This bit control data shift from lsb or msb. Set to 1, data is transferred from lsb
to msb. Set to 0, data is transferred from msb to lsb.
SPI Timeout Register Index F1h
Bit Name R/W Default
Description
7-0 TIMER_VAL
R/W 8’h04 The time in second to assert FWH_DIS signal when SPI in used as backup
BIOS.
SPI Baud Rate Divisor Register Index F2h
Bit Name R/W Default
Description
7-3 Reserved
-
0
1
Reserved
2-0 BAUD_VAL
R/W
This register decides to SCK frequency. Baud rate divisor equation is
33MHz/2*(BAUD_VAL).
00: 33MHz.
01: 16.7MHz.
SPI Status Register Index F3h
Bit
Name
R/W Default
Description
7
SPIE
R/W
R/W
0
-
SPI interrupt status. When SPI is transferred or received data from device
finish, this bit will be set. Write 1 to clear this bit.
6
FWH_DIS
When SPI is used as backup BIOS, this bit will set when time in second
reaches the value programmed in TIMER_VAL (CRF1). Write one to clear this
register.
When SPI is used as primary BIOS, this register will always be 1.
5
SPE
R
-
This bit reflects the SPI_EN register. (which will be 1 when SPI is enabled.)
95
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
