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F71862FG 参数 Datasheet PDF下载

F71862FG图片预览
型号: F71862FG
PDF下载: 下载PDF文件 查看货源
内容描述: 超级硬件监控+ LPC I / O [Super Hardware Monitor + LPC I/O]
分类和应用: 监控PC
文件页数/大小: 110 页 / 837 K
品牌: FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
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F71862  
3
2
1
0
PRT_PME_ST  
UR2_PME_ST  
UR1_PME_ST  
FDC_PME_ST  
R/W  
R/W  
R/W  
R/W  
-
-
-
-
Parallel port PME event status.  
0: Parallel port has no PME event.  
1: Parallel port has a PME event to assert. Write 1 to clear to be ready for next  
PME event.  
UART 2 PME event status.  
0: UART 2 has no PME event.  
1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next  
PME event.  
UART 1 PME event status.  
0: UART 1 has no PME event.  
1: UART 1 has a PME event to assert. Write 1 to clear to be ready for next  
PME event.  
FDC PME event status.  
0: FDC has no PME event.  
1: FDC has a PME event to assert. Write 1 to clear to be ready for next PME  
event.  
ACPI Control Register Index F4h  
Bit  
Name  
R/W Default  
Description  
7
TS3  
R/W  
0
Set to 1 into S1 state.  
Two wake up methods:  
1. PME wake up event Æ Must write this bit to 0.  
2. PS_OUT# wake up event Æ Auto clear this bit.  
6
5
SPI_RST_EN  
R/W  
R/W  
0
0
Set one to enable the reset signal from SPI via the PWROK or PCIRST#. (SPI  
as backup BIOS will assert a reset signal when FWH doesn’t response in 4  
seconds)  
KEY_SEL_ADD  
Set this bit one and KEY_SEL (CR2D[2:1]) 2’b00 will select windows 98  
wakeup key as keyboard wakeup key.  
4
3
EN_KBWAKEUP  
EN_MOWAKEUP  
R/W  
R/W  
R/W  
0
0
Set one to enable keyboard wakeup event asserted via PWSOUT#.  
Set one to enable mouse wakeup event asserted via PWSOUT#.  
The ACPI Control the PSON_N to always on or always off or keep last state  
00 : keep last state  
10 : Always on  
2-1 PWRCTRL  
11  
01 : Reserved (always on)  
11: Always off  
When VSB 3V comes, it will set to 1, and write 1 to clear it  
0
VSB_PWR_LOSS  
R/W  
0
ACPI Control Register Index F5h  
Bit  
Name  
SEL_S3  
R/W Default  
Description  
7
R/W  
0
1:selected by TS3  
TS3  
0: chip decided into S3 state from S3 pin  
1 : chip direct into S3 state  
0: chip decided into S3 state from VDD (VCC) power detect ok., which chip  
detects voltage circuit  
6
5
Reserved  
R/W  
R/W  
0
0
Dummy register  
RSTCON_EN  
0: Enable RSTCON# output via PWROK.  
1: Enable RSTCON# output via PCIRST#.  
99  
July, 2008  
V.28P  
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