F71862
Write serial data to this register correctly, the KEY_OK bit will be set to 1.
Hence, users are able to write key protected registers. The sequence to
enable KEY_OK is 0x32, 0x5D, 0x42, 0xAC. When KEY_OK is set, write
this register 0x35 will clear KEY_OK.
0
7-0
KEY_DATA
R/W
8.9.6
VIDIN Register Index F4h (04h) ( * cleared by slotocc_n and watch dog timeout)
Bit
7-4
3-0
Name
R/W Default
Description
Reserved
Reserved
R
R
0
-
VID_IN
Return the VID_IN status.
8.9.7
Watchdog Timer Configuration Register 1 Index F5h (05h)
Bit
Name
R/W Default
Description
Reserved
7
Reserved
R
0
0
If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to this
bit will clear it to 0.
6
WDTMOUT_STS
R/W
If this bit is set to 1, the counting of watchdog time is enabled.
5
4
3
WD_EN
WD_PULSE
WD_UNIT
R/W
R/W
R/W
0
0
0
Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.
Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit.
Select output polarity of RSTOUT# (1: high active, 0: low active) by setting
this bit.
2
WD_HACTIVE
R/W
0
Select output pulse width of RSTOUT#
1:0
WD_PSWIDTH
R/W
0
0: 1 ms
1: 25 ms
3: 5 sec
2: 125 ms
8.9.8
Watchdog Timer Configuration Register 2 Index F6h (06h)
Bit
Name
R/W Default
Description
Time of watchdog timer
7:0
WD_TIME
R/W
0
8.9.9
Output Voltage Control Register 1 Index F7h (07h) ( * cleared by slotocc_n and watch dog timeout)
Bit
Name
R/W Default
Description
Dummy register.
7-6
Dummy Reg
R/W
0
0
0: The VID registers is reseted when VDD power lose and watch dog
timeout.
5
REG_RST_SEL
R/W
1: The VID registers is reseted by slotcc_n and watch dog timeout.
Reserved
4
Reserved
R/W
R/W
0
0
Dummy registers.
3-0
Dummy Reg
94
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
