F71862
8.9VID Registers (CR07)
8.9.1
VID Configuration Registers
VID Device Enable Register Index 30h
Bit
Name
R/W Default
Description
7-1 Reserved
VID_EN
-
0
0
Reserved
0
R/W
0: disable VID.
1: enable VID.
Base Address High Register Index 60h
Bit Name R/W Default
Description
Description
7-0 BASE_ADDR_HI
R/W
00h The MSB of VID base address.
Base Address Low Register Index 61h
Bit Name R/W Default
7-0 BASE_ADDR_LO
R/W
00h The LSB of VID base address.
8.9.2
Bit
Configuration Register Index F0h (00h) ( * cleared by slotocc_n and watch dog timeout)
Name
R/W Default
Description
If this bit is set to 1 and watchdog timeout event occurs, WDTRST# output
is enabled.
7
WDOUT_EN
R/W
0
Return 0 when read.
6-3
2*
Reserved
OTF_EN
-
0
0
0
This bit is used to enable vid on-the-fly function.
Dummy register.
R/W
R/W
1:0
Dummy Reg
8.9.3
VID Offset Register 0 Index F1h (01h)
Bit
7:4
3-0
Name
R/W Default
Description
Reserved
VID offset. VID_OFFSET[3] is sign bit.
Reserved
VID_OFFSET
R
-
R/W
0
8.9.4
VID Manual Register Index F2h (02h)
Bit
7*
Name
MANUAL_MODE
KEY_OK
R/W Default
Description
If this bit is set to 1 and OTF_EN is 0, VIDOUT will be VID_MANUAL
R/W
R
0
-
This bit is 1 represents that the serial key is entered correctly.
Return 0 when read.
6
5-4
3-0
Reserved
R
-
VID_MANUAL
R/W
0
Manually assigned VIDOUT value
8.9.5
Bit
Serial Key Data Register Index F3h (03h)
Name R/W Default
Description
93
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
