F71862
Main Status Register Base + 4
Bit
Name
R/W Default
Description
7
RQM
DIO
R
R
0
0
Request for Master indicates that the controller is ready to send or receive data
from the uP through the FIFO.
6
Data I/O (direction):
0: the controller is expecting a byte to be written to the Data Register.
1: the controller is expecting a byte to be read from the Data Register.
5
NON_DMA
R
0
Non DMA Mode:
0: the controller is in DAM mode.
1: the controller is interrupt or software polling mode.
4
3
FDC_BUSY
R
R
0
0
This bit indicate that a read or write command is in process.
DRV3_BUSY
FDD number 3 is in seek or calibration condition. FDD number 3 is not support
in this design.
2
1
0
DRV2_BUSY
DRV1_BUSY
DRV0_BUSY
R
R
R
0
0
0
FDD number 2 is in seek or calibration condition. FDD number 2 is not support
in this design.
FDD number 1 is in seek or calibration condition. FDD number 1 is not support
in this design.
FDD number 0 is in seek or calibration condition.
Data Rate Select Register Base + 4
Bit
Name
R/W Default
Description
7
6
SOFTRST
W
W
0
0
A 1 written to this bit will software reset the controller. Auto clear after reset.
PWRDOWN
Reserved
A 1 to this bit will put the controller into low power mode which will turn off the
oscillator and data separator circuits.
5
-
-
Return 0 when read.
4-2 PRECOMP
W
000 Select the value of write precompensation:
250K-1Mbps
000: default delays
001: 41.67ns
2Mbps
default delays
20.8ns
010: 83.34ns
41.17ns
011: 125.00ns
62.5ns
100: 166.67ns
83.3ns
101: 208.33ns
104.2ns
110: 250.00ns
125.00ns
0.00ns (disabled)
111: 0.00ns (disabled)
The default value of corresponding data rate:
250Kbps: 125ns
300Kbps: 125ns
500Kbps: 125ns
1Mbps: 41.67ns
2Mbps: 20.8ns
1-0 DRATE
W
10
Data rate select:
MFM
FM
00: 500Kbps
01: 300Kbps
10: 250Kbps
11: 1Mbps
250Kbps
150Kbps
125Kbps
illegal
Data (FIFO) Register Base + 5
Bit Name R/W Default
Description
21
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
