F71862
These two bits indicate the DS1, DS0 bits in the command phase.
0
DS0
R
-
Digital Input Register (PC-AT Mode) Base + 7
Bit
Name
DSKCHG
R/W Default
Description
7
R
R
-
-
This bit indicates the complement of DSKCHG# disk interface input.
Reserved.
6-0 Reserved
Digital Input Register (PS/2 Mode) Base + 7
Bit
Name
R/W Default
Description
7
DSKCHG
R
-
-
-
This bit indicates the complement of DSKCHG# disk interface input.
Reserved.
6-3 Reserved
2-1 DRATE
R
10
These bits indicate the status of the DRATE programmed through the Data
Rate Select Register or Configuration Control Register.
0
HIGHDEN_N
R
1
0: 1Mbps or 500Kbps data rate is chosen.
1: 300Kbps or 250Kbps data rate is chosen.
Digital Input Register (Model 30 Mode) Base + 7
Bit
Name
R/W Default
Description
7
DSKCHG_N
R
-
-
-
This bit indicates the state of DSKCHG# disk interface input.
Reserved.
6-4 Reserved
3
2
DMAEN
NOPRE
R
R
R
0
This bit reflects the DMA bit in Digital Output Register.
This bit reflects the NOPRE bit in Configuration Control Register.
0
1-0 DRATE
10
These bits indicate the status of DRATE programmed through the Data Rate
Select Register or Configuration Control Register.
Configuration Control Register (PC-AT and PS/2 Mode) Base + 7
Bit Name R/W Default
Description
7-2 Reserved
1-0 DRATE
-
-
Reserved.
W
10
These bit determine the data rate of the floppy controller. See DRATE bits in
Data Rate Select Register.
Configuration Control Register (Model 30 Mode) Base + 7
Bit Name R/W Default
Description
7-3 Reserved
NOPRE
-
-
Reserved.
2
W
0
This bit could be programmed through Configuration Control Register and be
read through the bit 2 in Digital Input Register in Model 30 Mode. But it has no
functionality.
24
July, 2008
V.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
